The most common connecting structures between the functional units of circuits, in particular computers, are buses. Such a bus can be implemented either internal to a chip or between chips, for example as the system bus of a computer that exchanges data between the individual functional units. In the simplest case, the bus forms a node between line segments that realize the connections to the functional units with taps arranged in a star configuration. However, the bus arrangements of functional units described in summary by Kain in “Advanced Computer Architecture” (ISBN 0-13-007741-0), pp. 376-385 with the following topologies are also common: 1. individual point-to-point connection, 2. bus with bus controller, 3. multiple buses, 4. crosspoint switching system, 5. n-dimensional assigned functional units, 6. tree structures, 7. ring structures, 8. multilayer network with intermediate connections, 9. hierarchical structures.
To prevent information collisions from occurring on the bus, only one functional unit at a time may transmit its information onto the bus. To control such information exchange, the functional units are provided with interfaces which for the most part are mechanically and electrically specified, and are standardized, and thus ensure the time sequencing of allowed bus signals for the individual components.
The greatest disadvantage of prior art bus systems can be seen here in that only a single data transport can take place at any point in time. This leads to bottlenecks in data transmission on the bus, while the processing speed of the individual functional units is not fully utilized. Moreover, there are clear physical limits on improving utilization of the processing speed of the system by increasing the data transmission rate on the bus through increases in the computer clock speed.
Even the known prior art method of prefetching is only effective to a limited extent in achieving the desired utilization of the processing speed of the CPU, since the commands that are loaded in advance in this method must of necessity be discarded if the program conditions require it in the course of executing the program. As a result, the speed increase achieved is in part rendered ineffective in the processing of commands by the CPU.
Yet another method known from prior art, that of temporarily storing frequently needed recent commands, and also data, in a cache memory and thus avoiding additional data transmission across the bus, brings only a limited gain in increasing the processing speed of the CPU.
It is also necessary to mention a vector processor solution described in “Computer Architecture” by Michael J. Flynn (ISBN 0-86720-204-39), pp. 434-438. Here, data sets to be processed with the same operation, but which are prepared by different functional units, are combined in so-called vector registers. Within such a vector structure of specific length, these data sets are supplied as indexed blocks for processing with the required operation, e.g. ADD, MULTIPLY.
Thus, the greatest disadvantage in increasing the data transmission rate on a bus in prior art clearly consists in that it is not possible for functional units acting independently of one another to use the bus in parallel.
The object of the present invention is making it possible for functional units connected to a bus to communicate simultaneously and independently of one another.